WSCAD 2020

Abstract:

Transactional Memory (TM) is a simple, yet powerful, synchronization abstraction for concurrent programming, whose popularity has grown largely over the last years: nowadays, hardware supports for TM are provided in commodity CPUs (e.g., by Intel and IBM) and, at the software level, TM has been integrated in mainstream programming languages, such as C/C++ and Java.

Nowadays TM systems are faced with novel challenges and opportunities stemming from recent hardware developments, which have led to heterogeneity on two architectural fronts, namely memory and computing.

On the front of memory architectures, the emergence of Non-Volatile RAM (NVRAM) pushed storage one step closer to DRAM, promising higher density and comparable latency. In the near future, DRAM and NVRAM are expected to coexist, giving rise to a novel kind of heterogeneous memory architecture.

On the front of computing architectures, GPUs, and other massively parallel hardware coprocessors, have proven their importance in a number of data-intensive application domains. This has led heterogeneous computing architectures to become a mainstream solution adopted ubiquitously in systems ranging from smartphones to data centers.

In this talk I will focus on two challenges that affect state of the art TM systems when employed in modern heterogeneous memory and computing architectures, and present recent solutions that we developed to tackle these challenges.

The first problem is how to enable the employment of existing HTM systems over NVRAM --- a non-trivial issue given that the inherent limitations of available commodity HTM prevent the usage of classic techniques for transaction durability developed by the literature developed. On this front, I will present NV-HTM [1], a system that allows the execution of transactions over NVM using unmodified commodity hardware TM (HTM) implementations. NV-HTM exploits a hardware-software co-design approach that exploits two key novel ideas: i) relying on software to persist transactional modifications after they have been committed via HTM; ii) asynchronous checkpointing schemes that not only bound the log space and recovery time, but also implement wear leveling techniques to enhance NVM's endurance.

The second problem is how to allow CPUs and GPUs to cooperate synergistically within the same TM system, i.e., using the TM abstraction to synchronize concurrent accesses by CPU and GPUs to shared data structures. We tackled this challenge by introducing the abstraction of Heterogeneous Transactional Memory (HeTM) [2]. HeTM provides programmers with the illusion of a single memory region, shared among the CPUs and the (discrete) GPU(s) of a heterogeneous system, with support for atomic transactions. Besides introducing the abstract semantics and programming model of HeTM, I will present the design and evaluation of a concrete implementation of the proposed abstraction, which we named Speculative HeTM (SHeTM). SHeTM makes use of a novel design that leverages speculative techniques to hide the communication latency between CPUs and discrete GPUs and minimize inter-device synchronization overhead.

[1] D. Castro, J. Barreto and P. Romano, Hardware Transactional Memory meets memory persistency. Journal of Parallel and Distributed Computing, March 2019 (extended version of a paper previously appeared in the 32nd IEEE International Parallel & Distributed Processing Symposium (IPDPS), 2018. DOI: 10.1016/j.jpdc.2019.03.009
[2] D. Castro, P. Romano, A. Ilic and A. Khan. HeTM: Transactional Memory for Heterogeneous Systems, 28th International Conference on Parallel Architectures and Compilation Techniques (PACT 2019). DOI: 10.1109/PACT.2019.00026

Bio:

Paolo Romano received his PhD from Rome University "Sapienza" (2007) and his Master degree "summa cum laude from Rome University "Tor Vergata" (2002). Paolo is an Associate Professor at Técnico (U. Lisboa) and a Researcher at INESC-ID. His research interests include parallel and distributed computing, dependability, autonomic systems, performability modelling and evaluation, data management in large scale systems, cloud and high performance computing. In these areas, Paolo published more than 140 papers, receiving 3 best awards, and has coordinated several national and European projects, including a COST Action bringing together researchers from 60 institutions and 17 countries. Paolo serves regularly as Program Committee member and reviewer for renowned international conferences and journals, including EuroSys, DSN, ICDCS, MASCOTS, IEEE TKDE, IEEE TPDS, ACM TOPLAS.

Resumo:

A comparação de sequências biológicas é uma operação importante da Bioinformática pois determina o quão similares duas sequências são. Os algoritmos exatos que fazem essa comparação possuem complexidade quadrática e, portanto, demoram muito tempo, se as sequências comparadas são longas. Para acelerar a obtenção de resultados das comparações, as GPUs tem sido utilizadas há cerca de uma década.

Nessa palestra, serão apresentados inicialmente os algoritmos de Smith-Waterman e suas variantes, bem como a estratégia básica de paralelização desses algoritmos. A seguir, será discutida a ferramenta CUDAlign, que é uma estratégia paralela a grão fino, executada em clusters de GPUs, que usa as seguintes técnicas: execução em paralelogramo, execução ortogonal, poda de blocos (block pruning), sobreposição de comunicação e computação e especulação. Será mostrado que a ferramenta CUDAlign foi capaz de comparar sequências de DNA com até 249 milhões de caracteres em clusters com centenas de GPUs, obtendo o alinhamento ótimo.

A seguir, será apresentado um estudo de consumo de energia do CUDAlign multi-GPU e, por fim, discutiremos os trabalhos em andamento.

Bio:

Alba Cristina Magalhaes Alves de Melo possui Graduação em Processamento de Dados pela UnB (1986), Mestrado em Ciência da Computação pela UFRGS (1991) e Doutorado em Informática pelo Institut National Polytechnique de Grenoble (INPG), França (1996). Desde 1997, ela é professora do Departamento de Ciência da Computação da UnB, onde é atualmente Professora Titular. Prof. Alba é também Bolsista PQ nível 1C, Senior Member da IEEE Society e Membro da Sociedade Brasileira de Computação. De 2015 a 2019, ela foi Membro do Corpo Editorial do periódico IEEE Transactions of Parallel and Distributed Systems e atualmente ela é membro do Corpo Editorial do periódico IEEE Transactions on Computers e do Journal of Parallel and Distributed Systems. Ela foi Vice Program Chair da conferência IEEE IPDPS 2019 e é atualmente co-General Chair do IEEE International Workshop on High Performance Computational Biology (HiCOMB). Seus interesses de pesquisa incluem: Computação de Alto Desempenho, Bioinformática e Computação em Nuvem.

Abstract:

In the future of computing, we will have to support knowledge-centric systems, which will assist us in tasks like data interpretation, decision-making under uncertainty, scientific discovery, and design. These systems are continuously learning and have the human in the loop, either consuming knowledge and insights, or producing new knowledge in a structured digital form. In this presentation, we will explore some trends in this space and the research pursued in our group at IBM Research. On the one hand, we investigate new approaches and their supporting technologies to enable more symbiotic Human-AI interactions. On the other hand, we pursue research on technologies and their theoretical frameworks that support the co-evolution of symbolic knowledge representations and ML models. We will also discuss the interplay with the underlying compute platform that has to enable the right performance of these AI capabilities.

Bio:

Renato Cerqueira is Senior Research Manager at IBM Research Brazil, where he leads a research group that creates AI-based technologies for data interpretation and decision making, with focus on lifelong adaptive learning and reasoning, human-centered AI, knowledge engineering, and domain knowledge-augmented machine learning. Renato and his team have been exploring the application of their research to different problems in Geosciences, such as subsurface characterization and geological risk assessment. Prior to join IBM Research, Renato was professor at the Department of Informatics at PUC-Rio, where he pursued research in adaptive and reflective middleware technologies, and advised several Ph.D. and M.Sc. students. During 2001, he was Visiting Researcher at the University of Illinois at Urbana-Champaign, working with Prof. Roy H. Campbell on middleware technologies for Ubiquitous Computing.

Resumos:

^(†) Em uma economia cada vez mais competitiva e globalizada, inúmeros benefícios são obtidos quando uma organização se assegura de que é tecnologicamente independente, e sem o delay tecnológico típico de fabricantes proprietários, através do uso de infraestrutura baseada em padrões abertos.

^(‡) Pesquisadores de áreas diversas demandando soluções de computação científica, devem trabalhar em projetos mais e mais complexos e elaborados com o passar do tempo, produzindo a partir de massas de dados maiores a cada ano. Partindo-se dessa conclusão, vale conhecer as soluções de armazenamento mais adequadas para seus projetos. Para apresentar tais soluções, vamos explorar discos, SSD's e sistemas completos Seagate, que podem entregar a melhor relação custo / GB e os melhores números em latência, performance sustentada e endurance, entre outras especificações-chave. Porquê estamos todos inseridos em um mundo que deve produzir, segundo analistas, 175 Zetabytes de dados no ano de 2025, 10 vezes o volume de dados criado em 2016.

Bio:

Rodrigo Salomão é o CEO da Silix, fabricante com 15 anos de mercado. É responsável pela área de computação científica e HPC, com 23 anos de experiência em computação.

Osvaldo Junior é um Product Specialist na Seagate há 4 anos, responsável por capacitação e atendimento a parceiros de verticais diversas, tendo ministrado centenas de treinamentos e colaborado para o desenvolvimento de inúmeros projetos. Nos últimos 15 anos, atuou como instrutor / especialista de produtos, com passagens anteriores pela Asus e pela Intel.

Abstract:

The NEC SX-Aurora TSUBASA is the newest in the line of NEC SX Vector Processors with the high memory bandwidth. The Processor that is implemented in a PCI-e formfactor can be configured in many flexible configurations together with a standard x86 cluster.

In this talk, we introduce the NEC SX-Aurora TSUBASA, history, background and use cases.

Bio:

Noritaka Hoshi is Senior Manager of AI Platform division, NEC Corporation. He is responsible for product and business development of HPC systems, including SX-Aurora TSUBASA, LX systems, and software stack on these system. He has been engaged in research and development of HPC systems at NEC corporation for more than 20 years, including Earth Simulator, SX-ACE, etc.

Resumo:

FPGAs vem sendo utilizados em HPC em três grandes frentes: Aceleração de Computação, Armazenamento e de Rede. Veremos como a tecnologia pode ser usada nessas três áreas e também na aceleração de inferência para Machine Learning.

Bio:

João Dullius tem quase 17 anos de experiência em desenvolvimento em FPGAs, tendo atuado em áreas como telecomunicações, automação industrial e mais recentemente em datacenter e HPC. Desde 2013 é responsável pelo suporte da linha de FPGAs da Xilinx através da BP&M Rep.